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Whether it is for DDR, LPDDR, or GDDR, the topic of testing the memory PHY and the memory controller has recently been garnering significant attention in the industry. The reason is that, while the JEDEC specifications usually focus solely on memory device specifications, the performance of an entire memory system fundamentally depends on how effectively the controller and the controller’s memory PHY works. This is especially true for the latest generation of implementations that are starting to reach transfer rates of up to 28 Gbps. At these rates, the makers of memory controllers and memory PHYs are grappling with SerDes-style measurement requirements while not getting access to a solid set of test and measurement tools.

Introspect Technology has created a set of dedicated tools for DDR, LPDDR, and GDDR testing, which are ideal for solving the above industry conundrum! Read on to learn more about the challenges and the corresponding solutions from Introspect.

The Memory PHY Architecture

A generic memory PHY architecture is illustrated in Figure 1. As mentioned above, while the specific details of implementation differ slightly between the different memory interface variants (DDR, LPDDR, and GDDR), there is a common denominator as shown in Figure 1. Namely:

  • The memory controller / memory PHY has a source synchronous command and address bus, referred to below as CA for simplicity.
  • The memory controller / memory PHY has a bidirectional read/write bus, referred to below as DQ for simplicity.
  • The memory controller / memory PHY has a clock multiplication PLL (or several), and it is the source of all timing for both the controller itself and the memory. For example, the read strobe coming back from the memory (as shown in the bottom of Figure 1) is a signal that is derived directly from the PHY’s original clock.


Figure 1: A simplified memory PHY architecture.


From the above, we can see that there are multiple challenges with characterizing a memory PHY. But first, before even delving further into the details, refer to the pictorial illustration of Figure 2, which shows the evolution of transfer rates of memory PHYs over time. In this figure, we show a typical eye diagram from a memory PHY running at the maximum speed for any given generation of specification. Even with ideal conditions (as in Figure 2), it does not take many words to describe how the paradigm of testing current generation memory PHYs is so different from older generations!


Figure 2: Evolution of transfer rates of memory PHYs over time with ideal conditions.


With reference to Figure 1 and Figure 2, some of the challenges for the design and validation of memory PHYs include:

  • Measuring a true bit error rate on a fully parallel transmit bus (e.g. the CA bus or the DQ bus)
  • Characterizing crosstalk and equalization on a fully parallel transmit bus
  • Performing at-speed command decoding and error correction
  • Performing a fully parallel receiver stress test on the DQ bus
  • Understanding system-level phenomena including command spacing, memory payload, and training conditions

Test Setups Enabled by Introspect Technology’s ATE-on-Bench Solutions

CA Bus Setup

As mentioned in previous blog posts, such as this one about the MR-DIMM, Introspect has created a series of highly sophisticated solutions for the characterization and design validation of memory interfaces. Within the context of the memory PHY itself, Figure 3 shows how the CA bus is tested using the Introspect Technology SV7C-17 test system.


Figure 3: The CA bus tested using Introspect’s SV7C-17 test system.


As can be seen, the SV7C has enough pins to connect to an entire CA bus of any DDR, LPDDR, or GDDR memory PHY! What’s more, the receiver pins on the SV7C are all phase matched, and this allows for on-the-fly automatic measurement of skew as well as on-the-fly decoding of commands being transmitted from the memory PHY. Figure 4 and Figure 5 show examples of these respective measurements.


Figure 4: Automatic measurement of skew on a typical CA or DQ bus.


Figure 5: Decoding of commands being transmitted from the memory PHY.

DQ Bus Setup

Moving on to the DQ bus, this is where things get even more interesting because this bus is bidirectional. This means that there is a receiver test requirement, and once again, an Introspect tool like the SV7C-17 or SV7C-PAM3 is up to the task. Referring to Figure 6, a single SV7C-17 can interface to an entire DQ bus. In doing so, the SV7C-17 can perform true parallel testing on the receivers within the memory PHY. Until the SV7C-17 was introduced, this was a capability that was severely lacking in the industry.


Figure 6: The SV7C-17 can interface to an entire DQ bus.


The pattern handling capability of the SV7C allows the generation of arbitrary read burst data, and equally importantly, allows for the insertion of impairments at any location within a burst transmission. This is illustrated in Figure 7.


Figure 7: SV7C pattern handling capability which includes insertion of impairments.


Finally, Figure 8 shows an example receiver bathtub curve that is obtained directly from testing a memory PHY receiver. In this figure, we see the performance of the receiver under two conditions, one without jitter injection on the strobe signal, and one with jitter injection being inserted.

Figure 8: Receiver bathtub curve under two conditions.


The current generation of memory controller and memory PHY designs is expected to perform at levels that have never been seen before in the memory marketplace. Yet, there has been a largely ad-hoc approach to characterization and design validation in the industry. With the Introspect Technology tools, developers of memory PHYs or memory controller integrated circuits are able to gain deep insights into the performance of their chips, and this ultimately helps achieve higher success rates with system integration and interoperability with memory devices.

Ready to tackle your memory PHY testing challenges? Send us an email at today.


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