Three Differences Between GDDR7 and GDDR6 That Only an Engineer Will Appreciate!

The JEDEC Alliance just published the latest graphics memory specification, which is the Graphics Double Data Rate 7 SGRAM Standard (GDDR7) specification – JESD239. We couldn’t be more excited about this new standard because it deploys several serious technological innovations and advancements. These advancements naturally create seemingly insurmountable test challenges, and this is exactly why Introspect Technology exists. We’re here to help the industry cope with larger and larger technical hurdles.

While it is expected that GDDR7 will enable faster and larger memories, this article focuses on some of the technical aspects of the standard. It is a tribute to the engineers behind the standard and the decades-long research that has gone into advancing the graphics memory interface technology so far. So, here we go: the top 3 differences between GDDR7 and GDDR6 that only an engineer will appreciate!

1. PAM3 Signaling and a Higher Bit Rate Relative to Baud Rate

For as long as digital circuits have existed, computer architecture has relied on a binary representation of data. Every file we open, every video we watch, and every game we play is ultimately constructed by a vast river of 1s and 0s that flow between components within our computer or our smartphone. Moreover, electronically, these 1s and 0s have traditionally been represented by voltage levels: a high voltage represents a 1 and a low voltage represents a 0. In technical terms, this is a form of coding that is called pulse-amplitude modulation (PAM), and for the longest time, data has been transmitted over electronic circuits using a non-return-to-zero (NRZ) PAM signaling scheme consisting of only two levels.

To enable higher bandwidth, GDDR7 relies on another coding scheme called PAM3, and this is illustrated in the following figure.

As seen in Figure 1, this is another pulse-amplitude modulation scheme in which the number of levels to encode data is now three instead of two. That is, each clock period now encodes 2 bits of data instead of 1 bit. The benefit of having a larger-than-2 PAM scheme is increased throughput for a given clock rate. That is, a GDDR7 memory can send much more data within the same time duration that a GDDR6 memory can, but without having to run at a faster clock speed.

But PAM3 signaling is not the only innovation in GDDR7. Specifically, if we really wanted to transmit 2x the data for a given clock period, then we could have used a PAM4 scheme. At least in such a scheme, each voltage level would encode exactly two bits as shown in the figure below.

Just looking at the figure, we notice two things: a lot more transitions between voltage levels and a smaller voltage separation between the levels. Both of these phenomena increase the risk of bit errors in the transmission of data to and from the memory. So, GDDR7 sticks to only a PAM3 encoding scheme, and in addition, the standard uses a clever “burst” design and a clever symbol encoding to achieve a true 2x bandwidth improvement. Some of these techniques are too advanced to describe here. But you can see these techniques in action by using our M5512 GDDR7 Memory Test System.

2. Less Pins for the Command and Address Bus

The command and address (CA) bus is the digital connection between the graphics processor (GPU) and the GDDR memory. The GPU sends read and write commands to the memory over the CA bus, and it also sends the coordinates (address) for fetching data or storing data. Thus, it is critical to the operation of a GDDR memory.

As the industry transitioned from GDDR6 to GDDR7, the number of pins in the CA bus has been reduced dramatically! This means that for almost the same package size, more independent memory channels can be integrated. This allows for extra flexibility with using GDDR7 memories.

Figure 3 is only a simplistic illustration – please always refer to the exact pinout of your device before designing your hardware. But as you can see clearly, the GDDR7 standard enables further miniaturization in the industry by packing four channels of memory into a single package instead of only two.

3. New Read/Write Training Modes

Lastly, in DDR, LPDDR, and GDDR interfaces, training is a crucial step in making a memory work. Without training, the GPU or CPU would get wrong data from the memory due to PCB trace routing restrictions or environmental variations (e.g. temperature). In GDDR7, the JEDEC Alliance has introduced a number of new read and write training algorithms. These are designed to make the training step a bit more efficient and more rapid. For further details, please read the JESD239 specification.

We’re excited to see how GDDR7 accelerates AI and next generation technologies. The future is limitless and we’re here, ready to test every step. Are you grappling with the latest memory-related interfaces and need a test solution? Try us. Share your biggest test challenges at info@introspect.ca.