• Parallel (x16) jitter tolerance testing with per-lane jitter injection control
  • Per-lane voltage, skew, and noise injection control
  • Per-lane transmit and receiver equalization and per-lane hardware clock recovery (CDR)
  • Source-synchronous bus testing with auto-calibrated phase delays
  • State of the art programming environment based on the highly intuitive Python language
  • Single-ended or differential low-speed digital I/O for out of band device control
Popular solutions
PCIe Gen1, PCIe Gen2, DDR5, PCIe Gen3, JESD204B, PCIe Gen4
Maximum Per-Lane Data Rate

28 Gbps

Number of Lanes

16

Number of Signal/Data Analyzers

16

BENEFITS

  • Parallel (x16) jitter tolerance testing with per-lane jitter injection control
  • Per-lane voltage, skew, and noise injection control
  • Per-lane transmit and receiver equalization and per-lane hardware clock recovery (CDR)
  • Source-synchronous bus testing with auto-calibrated phase delays
  • State of the art programming environment based on the highly intuitive Python language
  • Single-ended or differential low-speed digital I/O for out of band device control

Features

The SV7C is a parallel high-speed tester that meets the emerging test and validation requirements of increasingly complex electronic component and board designs. Operating at up to 28 Gbps and featuring 16 independent pattern generators and 16 independent signal/data analyzers, the SV7C is an all-in-one, phase-aligned bit error rate tester (BERT) and protocol exerciser and analyzer, providing self-contained functional and physical layer test and measurement capabilities for interfaces such as PCIe, Ethernet, USB, and JESD204C.

The SV7C integrates multiple tools into one – a pattern generator with feed-forward equalization, an error detector with programmable equalization and clock recovery, a full-functional protocol exerciser, and a full-functional protocol analyzer. It provides unprecedented insights into crosstalk and channel-to-channel variations in highly parallel systems.

 

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