9 min
If you work at a CPU company or have worked at one in the past, you would probably be very familiar with the term “SLT”. If not, what is System-Level Test (SLT) and why is it so important? Join us on this short journey through the semiconductor manufacturing process to understand why System Level Test, or SLT, is so fundamental to manufacturing and shipping(!) semiconductor components.
To answer what system-level test is and why it is necessary, we must first talk about the transistor – oh, that incredible shrinking transistor. The transistor is the fundamental building block of any CPU, modem, amplifier, or wireless transceiver chip, and it is amazingly small. Figure 1 shows just how small the transistor can get! As can be seen from the figure, a single transistor in modern process nodes is almost 10,000x smaller than the width of a human hair. This is extremely small; you wonder how transistors are even produced at this nano-level scale. This leads us to the next topic, which is wafer processing.
Figure 1: Size comparison of some of the smallest particles in the universe.
Of course, transistors are combined to make useful logical functions. For example, a NAND gate is comprised of a connection of transistors as shown in Figure 2. And, as more and more processing is required (e.g. for AI), the number of transistors per chip grows exponentially. Today, it is possible to have more than 10 billion transistors per chip. That is, every chip has more transistors than there are humans walking on the face of this earth. And if you are a company making a consumer product such as a smartphone, then you will be manufacturing millions of these chips, each containing billions of transistors.
Figure 2: Four transistors make a 2-input NAND gate.
The best way to produce this kind of volume is through batch processing, which is what wafer processing really is. It is an extremely parallel process, and this is why the semiconductor industry relies on wafer processing as the most economical means for constructing chips.
For a good overview of wafer processing, check out this amazing article on Semiconductor Device Manufacturing Process, Challenges and Opportunities. We don’t need to get into the details here, but in short, the wafer processing flow starts with a semiconductor ingot that is sliced into wafers. Then, transistors are printed, etched, and doped onto each wafer using a technique that is very similar to how old photographic film is processed. By shining light onto a mask, some parts of the film are exposed to the light and some parts are not. The exposed parts react with the light to create the color on the photographic paper. This is how photographs were printed in the old days. And it’s almost how transistors are “printed” onto a wafer – just at a scale that is much finer than photographic film and using materials that are often much more exotic. Truly parallel, this process is a far cry from the 3D printer in your garage or home office.
Figure 3: Photograph of a semiconductor wafer.
Just like your ink jet printer might produce some smudges, streaks, or faint lines on the paper, the process of etching and doping a wafer is never perfect. And because transistors are so tiny, even the smallest of smears could cause an entire area of a semiconductor chip – or even an entire chip – to be completely damaged.
Figure 4 shows an illustration of how a defect can appear on a real circuit. The left panel shows the layout of the integrated circuit (viewed from the top). The transistors are connected together through higher-level metal layers, and the color coding just represents the layers of wiring metal above the transistors. The middle and right panels show a photograph of a real chip etched according to the design drawing of the left panel, and a defect is highlighted with a yellow circle. You can see the highlighted vertical “wire” has a bulge next to it, which wasn’t present in the layout drawing. Such a defect can sometimes be catastrophic (causing a short circuit), or it can be parametric (only altering the performance characteristics of the transistor) without causing a true short circuit. The topic of parametric faults is so important to system-level test, and it will be described further down.
Figure 4: An example of a defect that occurs during manufacturing. Source: P. Maxwell, et.al, “Cell-Aware Diagnosis: Defective Inmates Exposed in their Cells”, European Test Symposium (ETS) 2016.
The existence of defects is the reason we test chips, of course. However, the question: is how does a semiconductor company test a chip that has millions or billions of transistors? There is an entire science associated with this topic, and it all revolves around the topic of “test coverage”. How much testing do we need to perform in order to catch all probable defects or defect mechanisms? The next section describes the multiple test philosophies that have been adopted in the industry.
To maximize final yield, the industry generally performs at least three levels of manufacturing test, and these are described here.
This is the first test that is performed after a wafer is processed and before it is diced into individual chips. The goal of this test is to catch as many defects as possible in the shortest amount of time. For this reason, the tests at the wafer level tend to be structural in nature. They search for manufacturing defects, and they do not care about the functionality of the chip. So, even though the chip is indeed powered up and clocked during this test phase (while it is still on the wafer!), the types of vectors applied to the chip often look nothing like the functional vectors that play when the chip is deployed in its mission environment.
Note: with the increasing trend of selling chiplets as bare die, the topic of wafer-level test is receiving a lot of attention in the industry, and perhaps we will write an article about this in the future.
After the chip is diced and packaged, it goes through another test phase. This test phase verifies that package integration did not introduce any defects. But, this step also tries to add more tests that were not executed at the wafer level in order to increase coverage. So, while we still look for structural defects at final test, we also try to catch more subtle defects like the one in Figure 4. In that figure, the defect was labeled as a “bridge”, which means that it is not a complete short circuit. Rather, it adds parasitic resistance and capacitance, so it has the potential of severely degrading the performance of the chip. That is, the chip might work fine at low frequency, but it might fail as the clock frequency is increased. For this reason, some more “at-speed” tests are performed at the final test stage. This helps screen out some parametric defects.
You would think that after final test, the semiconductor device would be ready for shipping to its intended customer. But the reality is that there are still defects that are not covered by both wafer level test and final test. This is due to two main factors:
For these two reasons, the semiconductor industry needs system-level testing. This kind of test is almost a focused functional test that mimics the target application of the device. For example, if the device is a smartphone CPU, then system-level test means putting the device on a representative smartphone motherboard and booting it up with the operating system. Similarly, if the device is a flash memory going into a USB thumb drive, then the SLT setup for this device would literally be a PC with the appropriate drivers for the chip.
From the above, you can see that a system-level tester is almost a custom platform containing a smartphone, a PC, or whatever platform on which the device under test is intended to be used. For this reason, SLT testers are often custom systems, and they are often designed internally by the semiconductor company itself.
When engineers design their own in-house system-level tester, they face a lot of challenges related to cost and miniaturization, and this is where Introspect helps. Introspect Technology’s E Series products are compact modules that can be integrated into an engineer’s own tester design. They provide instrument-grade stimulus and capture capability for various interfaces under test. For example, if the customer DUT needs a camera stimulus, then the SV4E-DPTXCPTX product can be programmed to operate as if it was a commercial camera, with any resolution and any frame rate. This makes it ideal for integration into a system-level tester. It allows the customer to “mimic” different camera vendor models without having to keep buying cameras and designing them into the SLT tester. Similarly, our products can be used for display interfaces or memory interfaces as well.
Figure 5: SV4E-DPTXCPTX MIPI Transmit Device Emulator.
The semiconductor industry’s fascinating ability to mass produce chips containing billions of transistors has been described in this article. Additionally, we described the test phases needed to ship the produced products, and we showed how SLT is so critical as the final step before a chip can be shipped to intended customers. It is no exaggeration to say that SLT is one of the most important steps required before shipping products. At Introspect Technology, we are happy to supply our E Series modules as subsystems that can be integrated into our customers’ SLT tester designs.
Do you design your own system-level tester? Reach out to us at info@introspect.ca.
