Why You Need a Massively Parallel BERT for LPDDR6 Validation

New LPDDR6 memory devices are currently being designed into system implementations for both mobile applications as well as server applications. Building on the learning experiences from previous generation LPDDR and DDR interfaces, the industry is now doubling down on the test and validation methodology for LPDDR6, and this can have an unprecedented impact on your lab and bench environment! Introspect is here to help with solving this urgent and emerging conundrum, so read on to learn about the challenges of LPPDR6 Bit Error Rate Testing (BERT) and also about how the M Series ATE-on-Bench / Massively Parallel BERT can help.

High-Level Block Diagram of a LPDDR6 Interface

Figure 1 shows a high-level block diagram for LPDDR6. A single memory channel consists of two groups of distinct pins. First – shown in the blue section of the figure – is the command bus (also known as the CA bus). This is typically unidirectional, and it is the bus that helps a memory controller send commands to a memory device. Then – shown in the orange section of the figure – there is the data bus (also known as the DQ bus), and this is the conduit over which write and read data are transferred between a memory device and a memory controller. This bus is typically bidirectional.

Figure 1: Simplified illustration of LPDDR6 memory interface.

The LPDDR6 Test Challenges

Electrical Test Challenges

While LPDDR6 massively improves memory bandwidths and other performance metrics, it puts immense pressures on ensuring high production yields. The following is a summary of the challenges that LPPDR6 brings to electrical testing using a BERT:

• High speed operation: LPDDR6 is blisteringly fast. While it may be argued that most chip-to-chip interfaces now operate at speeds that reach the tens of Gigabits per second per pin, the speed challenge of LPDDR6 is decidedly unique, especially in light of the specification constraints of the standard, elaborated on next.
• Single-ended: unlike interfaces such as PCI Express or USB, the LPDDR6 interface is still single-ended, and it still operates at very low voltages. When you couple this with the density of pins in a single memory package and the severe impact of crosstalk, the single-ended nature of LPDDR6 means that the interface must be tested in parallel!
• Bidirectional: yes, not only is the LPDDR6 data bus operating at very high speeds and not only is it single-ended, but it is also bidirectional, and its turnaround time is measured in nanoseconds, not microseconds nor milliseconds. This makes testing very difficult because most BERT architectures are slow.
• Source-synchronous clocking: this means that any BERT solution must support source-synchronous pattern generation and source-synchronous capture, something that most BERTs in the industry do not currently support.
• Burst-mode transmission: finally, as if the above challenges are not difficult enough, LPDDR6 – just like previous generation memory interfaces – relies on extremely short bursts. The burst lengths are measured in nanoseconds, not microseconds nor milliseconds, and this means that conventional BERTs that rely on clock and data recovery (CDR) cannot be used for testing this interface!

Figure 2 below summarizes the electrical test and validation challenges for LPDDR6.

Figure 2: Summary of the electrical validation challenges of LPDDR6.

Protocol Test Challenges

Perhaps more important than all of the above challenges is the fact that for a LPDDR6 interface to be tested even at the electrical level, it needs to be trained first! And training happens through a somewhat complex protocol interaction. Namely, the following challenges need to be addressed:

• Command bus and data bus training: just to be able to send commands (including test mode commands) to the LPDDR6 device, the interface must be trained. And training occurs across an entire memory bus, not just one pin!
• Training requires feedback from the data bus: moreover, when a training command is sent over the CA bus of the LPDDR6 device, the response from the DUT often comes back on the DQ bus. A BERT that performs training on a LPDDR6 device must have enough pins to cover both the CA bus and the DQ bus!
• Encoding and data integrity: as the speeds have increased, so also has the need to add some limited encoding and metadata to the LPDDR6 protocol. Burst data now does not only consist of simple read and write data, but it also contains additional data. A BERT performing a test on a LPDDR6 device must be able to deal with these new data fields!

Figure 3 below shows a summary of the protocol validation challenges of LPDDR6, and Figure 4 highlights the specific training challenge with LPDDR6 – a challenge that requires the BERT to have an incredibly large number of channels.

Figure 3: Summary of the protocol validation challenges of LPDDR6.

Figure 4: A massively parallel BERT is required to connect to both the CA bus and the DQ bus of a LPDDR6 interface.

Introspect’s M Series as a Massively Parallel BERT

The M Series introduces a new class of massively parallel high-speed testers that are ideal for functional validation, high-volume data collection, and characterization. These systems provide bench-grade measurement accuracy and precision, but at a scale that is not possible using conventional BERT solutions. At the same time, they are programmed and operated like automatic test equipment (ATE), enabling full functional, at-speed testing.

The hybrid nature of the M Series – part BERT, part ATE, part system-level tester – makes it ideal for LPDDR6 testing. And in the context of parallel BERT connectivity, the system comes with a standard coaxial cable interface as shown in Figure 5.

Figure 5: Photograph of the M Series illustrating the coaxial cable interface, just as expected of a bench BERT setup.

Each pin on the M Series is a fully programmable BERT channel, and it is capable of performing both pattern generation and pattern detection functions. Most notably, being a BERT, each channel is capable of introducing various impairments for receiver stressed eye testing. A small sampling of the kinds of impairments that can be introduced is shown in Figure 6 below.

Figure 6: Subset of the impairment generation of each channel on the M Series Test System.

Summary

There you have it: LPDDR6 is here, and it requires a large number of BERT channels in order to be tested. In this article, we described how electrical testing requires a special breed of BERT equipment, and we also showed how protocol training requires what we call entire-bus connectivity with a BERT. Finally, we introduced Introspect’s M Series tester and how – in the context of LPPDR6 testing – it can behave as a massively parallel BERT, enabling both electrical validation and functional validation.

Working on a LPDDR6 project or a project that needs a massively-parallel BERT? Our team at Introspect Technology is ready to help. Reach out at info@introspect.ca to discuss your design challenges and discover how our tools can make for seamless validation.