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In 1999, John Goldie, a pioneer in LVDS technology and also a good friend of Introspect Technology, published an article titled “LVDS Goes the Distance!”. Now 25 years later, we could not come up with a better title for our article, so here is Introspect’s tribute to LVDS and to our good friend John. Read on to learn about LVDS automotive display technology and how it is tested!

Which LVDS?

The acronym LVDS stands for “Low Voltage Differential Signaling”, and because of its success and ubiquity, this term has been used to describe so many interface technologies. If you think about it, most high-speed interfaces use low voltage differential signaling, and these include PCI-SIG’s PCI Express®, VESA’s DisplayPort™, MIPI Alliance’s D-PHY℠ and M-PHY®, and many others. So, it is easy to lose track of which interface one is talking about when we simply use the term “LVDS”. In this article, we’re interested in the original LVDS standard which is used in display links, and this is sometimes called LVDS Display Interface (LDI) or Open LVDS Display Interface (OLDI). We describe some of the characteristics of the Open LVDS Display Interface (OLDI) in the next section.

Introduction to the Open LVDS Display Interface (OLDI) Technology

Physical Layer

The OLDI interface relies on the original LVDS physical layer, which had two distinct characteristics. First, the driver is a current-mode design that has a current source biasing two complementary transistors as shown in Figure 1. The second characteristic of LVDS is that it is a DC coupled link with a single floating 100 Ohm floating termination resistor at the receiving side. This is also shown in Figure 1. The use of the floating termination makes biasing an LVDS link somewhat easy. Additionally, the current-mode design means that the common-mode level of an LVDS signal is relatively high by today’s standards, sitting at 1.25 V.

Figure 1: LVDS physical layer.

Pixel Transport Layer

To transmit pixel data serially across an LVDS differential pair, the OLDI protocol relies on parallel to serial conversion (also known as serialization) and running multiple differential pairs in parallel. For example, to send 24-bit RGB data across 4 differential pairs, the OLDI protocol would create a transmission timing diagram like the one shown in Figure 2.

Figure 2: Transmission timing diagram.


A salient feature in the above timing diagram is that there is a forwarded clock that is used to synchronize the data transmission between the source of the video and the receiver. That is, one extra differential pair is used to transmit a clock signal. Additionally, this clock signal is typically 7x slower than the data being sent. There is a 7:1 ratio between the data lanes and the clock lane. This helps with signal integrity and with pixel clock synchronization on the receiver side.

From a design point of view, the above timing diagram translates into a design block diagram similar to the illustration in Figure 3. Importantly, there is a need for phase locked loops (PLLs) on both the transmitter side and the receiver side of an OLDI link.

Figure 3: Design block diagram.


In addition to the PLLs, you can notice that the digital fabric driving an LVDS display interface is very light, and it does not include complex encoding, mapping, or scrambling logic. This is perhaps one of the biggest appeals of the OLDI standard for the creation of very low-cost display implementations. This explains why LVDS displays are currently very popular in automotive technology.

Testing and Characterizing OLDI Receivers in Automotive Displays

In modern-day implementations of OLDI displays, engineers are creating display systems with a large number of simultaneous OLDI links. It is not unheard of to see a single display solution containing 4 LVDS ports of 4 lanes each or more. To characterize such implementations, a flexible pattern generator is needed, and the Introspect SV3C-12 Personalized SerDes Tester is the ideal product for this. It has up to 32 pattern generators integrated into a small form factor, and it is able to perform clock-to-data skew injection as well as jitter injection. An example of how the SV3C-12 is used for OLDI receiver testing is shown in Figure 4 below.

Figure 4: Diagram of the SV3C-12 used for OLDI receiver testing.


In this figure, we see multiple components, and these are described next.

SV3C-12 Pattern Generator

The SV3C-12 SerDes Tester is the main component of the OLDI characterization solution. Although it has receivers, the usage of the SV3C-12 in this application is for pattern generation only. Each lane has its own pattern generator memory, and the Pinetree software is used to create a ready-made OLDI video generation interface.

In addition to the protocol API for generating OLDI video data, the SV3C-12 supports programmable voltage swing, programmable clock to data skew with picosecond resolution, and programmable jitter injection. It can thus be used for characterizing receiver sensitivity and jitter tolerance. The jitter tolerance test is very important for making sure that the PLLs inside the receiver are all working well.

Common-Mode Controller

The SV3C-12 has an optional common-mode controller peripheral, and two of these are shown in Figure 4. This peripheral receives the pattern generator data from the SV3C-12, and it adds arbitrary common-mode voltage offsets on it, thus allowing the SV3C-12 to test interfaces at voltages much higher than the 1.25V required by OLDI. Additionally, each lane can be programmed with its own common-mode voltage, thus enabling a truly flexible characterization paradigm. For example, the clock lane common-mode voltage can be swept while holding the data lanes at a constant level or vice versa.

PC With Pinetree Software

Finally, the key to automating all tests is Pinetree. Referring to Figure 5, we see the built-in API for OLDI pattern generation. Following a familiar architecture to our other display characterization solutions such as MIPI DSI-2 and VESA DisplayPort, the software provides a hierarchical representation of the pattern generator with components for pattern generation, data rate control, and common-mode control.

Figure 5: Built-in API for OLDI pattern generation in the Pinetree software.



There is something timeless about LVDS displays. Perhaps it’s the evergreen acronym “LVDS” and perhaps it’s the somewhat simple protocol relative to the high performance. Whatever it is, there is a range of multi-port display solutions that is currently being implemented, and Introspect is here to help! With our highly parallel pattern generators, we’re able to provide the industry with a highly flexible and cost-effective test and characterization solution. Send us an email at with all your LVDS testing questions.


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