6 min
The transmission and reception of images is a key operational feature of most modern electronics. Smartphones, tablets, cameras, watches, laptops – even the most advanced coffee machines – all consist of sources and sinks for image data in some form. Understanding how this data is transmitted between the various components of a device (e.g. between a camera and a processor) is thus a key part of the design and validation stages of any product.
This article aims to break down some of the key concepts used in digital image transfer. We present these concepts through standards laid out by the MIPI Alliance which has defined some of the most commonly used image transmission protocols in the industry.
Operation Modes: Low Power (LP) vs High-Speed (HS)
Transmitting a picture electronically entails converting each pixel of an image into binary data (0’s and 1’s) and then transmitting this stream of bits as a series of electronic pulses. This is typically accomplished by sending a time varying voltage across a conductor, or a signal, that swings between two levels. The high voltage represents a ‘1’ and the low represents a ‘0’. The electrical characteristics of the signals are defined by industry standards such as MIPI D-PHY.
There are two main modes in which bit transmission or signaling takes place: Low power (LP) and high-speed (HS):
Low Power (LP) Mode:
This mode is characterized by a large voltage swing (1.2V), single-ended signaling, and minimal static power consumption. It is used to conserve battery life when not transmitting image data and to transfer control information at low bit rates (order of Mb/s).
High-Speed (HS) Mode:
High-speed signaling is differential and characterized by a small swing voltage (200 mV). It is used for fast transmission of image data (order of Gb/s). The low voltage swing helps offset the heavy power consumption requirement of the high switching rate.
Anatomy of a Burst
A burst refers to the transmission of high-speed serial data. The transmission of an HS burst starts and ends with an LP state. So, in practice, if one were to ‘look’ at a picture being transmitted, one would see a series of LP-HS transitions. How does this appear visually? An example of an analog image capture using Introspect’s SV5C-CPRX MIPI C-PHY Analyzer is shown below:
While this signal capture might look rather simple, each section of the burst is meticulously defined by standards and it is a validation engineer’s job to ensure each part of the burst is within the specification. For example, in the D-PHY protocol, the sequence to enter the HS burst mode is the series of LP states: LP-11, LP-01, LP-00 (LP-11 means that the P and N wires are in the logical ‘1’ state respectively, which is typically 1.2V. LP-00 means both are in the logical ‘0’ state). The transmission on the line continues in high speed mode until another LP-11 state is sent, which signals the stop state. This pattern of LP-HS-LP transitions can be seen more clearly in the schematic below which indicates the various sections of the burst sequence:
PHY Layer Vs Protocol Layers:
Protocols governing the communication between electronic peripherals can be categorized in two stages: PHY-level and protocol-level. The difference in the two is summarized below:
PHY Layer:
PHY refers to the physical layer which connects the electrical components and is at the lowest level operationally. PHY specifications define how a stream of bits is converted to a physical signal sent over the transmission medium, e.g. a copper trace. The electrical and functional characteristics of the signal, procedures for indicating start/end of transmission, timing relationships between clock and data lanes are specified by the PHY standard.
Protocol Layers:
Digital data is organized into packets of information and transmitted over the PHY layers. A packet is a group of bytes organized in a specified way. The protocol layer is a high-level layer that defines the structure of the packets transmitted over the PHY; one PHY can support different protocol layers. Packetization protocols, such as CSI-2 and DSI-2, specify the size, header, payload and error-correction information for each of the packets. Figure 4 below shows an example of a digital image capture, taken with the SV5C-CPRX MIPI C-PHY Analyzer, which features a comprehensive view of packet-level information.
D-PHY vs C-PHY
Two of the most commonly used PHY-level protocols are C-PHY and D-PHY. While both specifications are designed to offer fast data transmission across multiple lanes, there are some key conceptual differences between the two configurations.
D-PHY transmission takes place typically over four data lanes and one clock lane. The minimum configuration requires one clock lane and one data lane. There are two wires per lane (positive and negative); the minimum configuration thus requires 4 wires. Data transmission takes place at an efficiency of 1 bit/UI and can reach speeds of 2.5 Gbps / sec (D-PHY v1.2).
C-PHY is a more sophisticated standard and it eliminates the need for a separate clock lane by embedding the clock into the data. In C-PHY, lanes are called trios and each trio consists of three wires, where each wire is capable of three-level signaling (low, mid, high). The data is encoded into special symbols which each contain 2.28 bits of information. Transmission is thus more efficient at 2.28 bits/UI which allows for C-PHY transmission to reach higher data rates with lower toggle rates. Data rates for C-PHY are often quoted in symbols per second as opposed to bits per second.
Conclusion
Whether you’re a validation engineer, or you’re on your way to becoming one, these four MIPI image transmission concepts are the foundation for what a validation engineer should know. In addition to creating ultra-portable solutions that simplify the tasks for engineers in the test and measurement space, it’s also our mission to empower engineers through educational resources like this article.
Are you eager to know more about these image transmission concepts? Are you facing any real-life challenges regarding these concepts? Connect with us at info@introspect.ca.
