This article was originally published by All About Circuits. You can find the original article here.
FEBRUARY 16, 2024 BY DUANE BENSON
Introspect Technology Introduces LPDDR5/LPDDR5X Protocol Analyzer
The analyzer’s package-on-package interposer design enables shorter cables and active probing with measurements at 8,533 MT/s or more.
Low-power double data rate 5 (LPDDR5) memory is the highest-performance memory option today for mobile devices. It delivers the same high speed as conventional DDR5 but trades off density, upgradability, and DDR5’s dual-channel topology for features that benefit mobile devices, such as lower power consumption. The latest version of the standard, LPDDR5X, introduced by JEDEC in June 2021, delivers additional speed and even lower power consumption than standard LPDDR5.
Introspect Technology recently released the model SV7M-LPDDR5PA Protocol Analyzer to offer compliance verification, deep analysis, and debugging in a live LPDDR5 system.
LPDDR5 Constraints Require Creative Access Solution
LPDDR5 performance gains are not only realized within the memory chip but also in the required physical product design. Current incarnations of LPDDR5 must be placed as close to the CPU as possible and must be soldered in. In a mobile device, the memory is often soldered directly on top of the CPU in a package-on-package (PoP) arrangement.
In PoP, the CPU has BGA solder balls on the bottom and solder pads on top to receive the memory chip. It is soldered onto the printed circuit board, and the memory chip, also a BGA, is soldered to the top of the CPU, resulting in a birthday cake-like stack where the chip pins are not accessible beyond the outer rows. Introspect solves the problem with an interposer PCB. The interposer sits on top of the CPU and has the LPDDR5 memory chip on top of the PCB.
Key Features and Benefits
The SV7M-LPDDR5PA supports one complete channel, both command and data bus, of LPDDR5 and LPDDR5X at up to 8700 mega transfers per second (MT/s). It supports command capture decoding and analysis for LPDDR4, LPDDR5, LPDDR5x, and DDR5.
The modular design includes remote sampling heads (RHS) placed close to the device under test to enable complete data and command capture. These RSH sampling heads have 10-GHz bandwidth active probes for all 32 channels, delivering high-bandwidth measurements and reduced interposer losses. The analyzer also features triggered one-shot digital capture on command and data buses in parallel for simultaneous electrical and protocol validation with the same RSH and interposer.
Some other notable specs of the SV7M-LPDDR5PA include 32 differential or single-ended receivers to cover a full LPDDR5 channel (including the command bus and the 16 data pins) and 12 GPIO pins to auto-calibrate all RSH units. The analyzer can trigger on any of ACT1, ACT2, CAS, DES, MPC, and all commands in the LPDDR5 truth table.
In-Place Testing
Low-power DDR5 is targeted for applications where space and power are restricted, such as mobile devices and automotive computing. As such, most implementations are not socketed or modular in any way. Further, LPDDR5 speeds require that users exercise extreme care when using this memory technology to avoid compromising the signal integrity with the test equipment. These conditions make interposing socket or cable systems impractical or impossible to implement.
The interposer PCB directly routes all chip pins from the CPU to memory, reducing the chances of signal degradation. The interposer PCB taps all the necessary signals, which are terminated with active probe tip resistors. The board directs these signals to connectors for remote sampling heads, giving access to the necessary data and control lines. The system aims to be a high-quality analysis tool that considers both the component requirements and the restrictions of its operating environment.
All images used courtesy of Introspect Technology.