Title: Advanced Topics in DDR5 Testing
Date: Thursday, March 26, 2020
Time: 11:00 – 12:00 EDT
Join us for this complimentary webinar to learn some of the more advanced topics related to training and functional testing for JEDEC® DDR5 standard components and systems.
Why This Event Was Important
Representing an almost complete re-architecting of the memory channel, the DDR5 standard introduces several significant changes over the previous generation DDR4 standard. This webinar explains – in detail – some of the more complex training sequences required by DDR5 as well as the functional test scenarios that present significant challenges to architects, designers, and test engineers. We will show how achieving full coverage of the many training and operating modes of next-generation DDR5 memory systems requires an equally modern test solution that is protocol capable, provides flexible stimulus generation, and applies sophisticated capture and measurement techniques.
- Initializing and training the DDR5 command and data buses
- Calibrating write latencies
- Measuring read latencies
- PDA enumeration
- Key building blocks for enabling functional testing
- Capturing and analyzing read data bursts
- Data and strobe bus turnaround
System architects, digital design engineers, verification engineers, product engineers, test engineers, applications engineers, system integrators, product line managers, and project managers.
Senior Member of Technical Staff, Introspect Technology
Erin specializes in digital design and system architecture as part of Introspect Technology’s R&D team. She currently leads the development of test solutions for high-speed memory interfaces at Introspect Technology.
Register for this event here.