Date: Wednesday, March 13, 2019 at 11:00 EST – 12:00 EST
This complimentary webinar allowed attendees to take a deep dive into the MIPI® I3C℠ interface and its features as well as to learn about the latest trends and best practices in the design and verification of this emerging industry standard.
Why This Event Was Important
The MIPI I3C interface standard promises to deliver significant advances in the domains of digital sensor communications and multi-sensor data processing algorithms. Achieving a reduced pin count when compared to legacy control bus standards, this standard offers an order of magnitude improvement in bandwidth, a decrease in power dissipation, and an entire slew of programmable features that enable the integration and inter-operation of truly diverse sensor/device classes on a single bus.
Understanding the origins of the I3C standard as well as its multiple operating modes and protocol-level interactions is critical to achieving first-time success with new semiconductor devices based on this exciting new bus standard. Similarly, creating embedded products housing I3C-enabled devices is much accelerated with the proper handling of protocol subtleties related to device roles, hot-plugging (hot joining), and command codes.
The following topics were discussed:
- Fundamentals of the I3C bus
- Comparison to the more familiar I2C bus
- Understanding I3C device roles
- Exercising slave devices
- Exercising master devices
- Probing complete buses
System architects, digital design engineers, verification engineers, product engineers, test engineers, applications engineers, system integrators, product line managers, and project managers.
View the Recording of the Webinar
You can view the recording of the Enabling the Design and Test of I3C-Based Devices webinar here.