Santa Clara, USA, January 29, 2019 — Introspect Technology, manufacturer of innovative products that address the entire multi-Gbps test and measurement instrument experience, today announced the release of a complete test and characterization solution for fifth generation double-data-rate (DDR5) memory interface applications which is based on the company’s SV5C Personalized SerDes Tester. With the release of its fifth-generation DDR solution, Introspect Technology has proven yet again that the company can be relied on to provide its customers with innovative solutions for high-speed, high-channel count interface technology.
The SV5C is a protocol- parallel BERT solution that allows for gaining deep insights into multi-channel interface link performance including DDR4 and now DDR5 links. The new DDR5 solution is comprised of a set of both software and hardware extensions to the SV5C. On Wednesday, January 30, 2019 and Thursday, January 31, 2019, the public will get the opportunity to watch demos of Introspect Technology’s highly parallel pattern generator and signal analyzer solutions for DDR5 interface tests at the free DesignCon expo (booth 422), taking place at the Santa Clara Convention Center.
“True to Introspect Technology’s tool development approach, our solution is ultra compact, high performance, and completely protocol capable — and we’re excited to be supporting JEDEC (Joint Electron Tube Engineering Council) this way,” stated Dr. Mohamed Hafed, Chief Executive Officer of Introspect Technology. “As DDR5 development proceeds, the memory interface sector is transitioning to ‘extreme’ receiver and transmitter eye characterization requirements that are currently being defined by the JEDEC alliance. Our solution is becoming central to the ecosystem because it covers these requirements across a large number of channels simultaneously and efficiently,” he continued.
All-New Additions Achieve Fifth-Generation Requisites
When it comes to building the latest generation DDR interfaces, developers face unprecedented challenges during both the design verification and interface characterization phases. With the SV5C, Introspect Technology has added features which successfully achieve the stringent requirements including:
- Single-ended signaling at data rates that far exceed the JEDEC specifications for DDR5 — an invaluable addition as this gives users a great deal of headroom in terms of measurement accuracy;
- Large channel count covering entire Registered Clock Driver (RCD), dynamic random-access memory (DRAM), Data Buffer (DB), and module buses in an ultra-small footprint, rendering the SV5C the smallest multi-channel characterization solution in the industry by far;
- Precision, per-channel skew control and matching with picosecond resolution and accuracy — a unique feature that can open new possibilities in system-oriented test methodologies;
- Per channel jitter injection, thus enabling receiver stressed eye testing with coverage for CTLE and DFE responses;
- Protocol-based traffic generation and automated training, including write leveling and calibration;
- Parallel, simultaneous Tx waveform measurement and analysis enabling accurate setup and hold time measurement; and
- Support for the multiple JEDEC loopback modes.
SV5C’s Flexibility is Key for Testing Increasingly Complex Memory Interfaces
Not only is memory technology exceedingly important for powering our servers and data centers, but it is also critical for machine learning and artificial intelligence (AI). The reason is that, whereas conventional programming relies on algorithm development, machine learning relies on enormous amounts of data — data that is stored in DRAM or non-volatile memory and that must be transported at very high speeds. In turn, the higher level of memory system performance necessitated by these applications results in more demanding validation processes; devices under test (DUTs) including DRAMs, RCDs, DBs, controllers, modules, and systems each have their own sets of unique test requirements and validation models. To name a few, memory component and system designers must perform device characterization tests, module and incoming inspection tests (or acceptance tests), , system characterization tests, and host emulation. Out of these, Introspect Technology’s SV5C tester especially excels in host emulation, creating a system-on-bench architecture in which the SV5C tester can be used to emulate a host while still generating analog stress conditions like skew, jitter, and closed eyes. For example, the Introspect Technology DDR5 solution can initialize a memory module through its protocol control bus (SMBus), initiate CS and CA training, and enable loopback mode while running analog characterization loops and without requiring additional components.
For hardware to successfully meet the high bandwidth and high capacity requirements of machine learning and AI, the performance of measurement technology is indispensable. And with the increasingly important role of DDR memory technology in the advancement of machine learning and AI, Introspect Technology’s SV5C for DDR5 applications is the obvious choice of tool for developers — a complete solution that will help implementers of memory interfaces realize the design targets set forth by the industry.
The SV5C Personal SerDes Tester is available for purchase from Introspect Technology or through one of its approved worldwide distributors.
About Introspect Technology
Introspect Technology offers the most extensible measurement and optimization tools for high-speed digital product engineering teams worldwide. portable, software-defined instruments deliver unprecedented productivity enhancement throughout all stages of multi-GHz product development: from bring-up characterization to system-level integration and optimization. Our mission is to enhance competitiveness, product quality, and time-to-market for our customers.