• True parallel bit-error-rate measurement across 8 lanes
  • Programmable data rate selection from 39.2 Gbps – 58 Gbps
  • Programmable output voltage on all transmitter lanes for receiver stress test applications
  • Fully synthesized integrated jitter injection on all transmitter lanes
  • Two-tap pre-emphasis control on all transmitter lanes
  • Hardware clock recovery per lane
  • Flexible loopback support per lane
  • Support for both PAM4 and NRZ data patterns
  • State of the art programming environment based on the highly intuitive Python language
Popular solutions
PAM4, NRZ, GbE
Programmable Data Rate

39.2 Gbps – 58 Gbps

Number of Lanes

8

Number of Signal/Data Analyzers

8

BENEFITS

  • True parallel bit-error-rate measurement across 8 lanes
  • Programmable data rate selection from 39.2 Gbps – 58 Gbps
  • Programmable output voltage on all transmitter lanes for receiver stress test applications
  • Fully synthesized integrated jitter injection on all transmitter lanes
  • Two-tap pre-emphasis control on all transmitter lanes
  • Hardware clock recovery per lane
  • Flexible loopback support per lane
  • Support for both PAM4 and NRZ data patterns
  • State of the art programming environment based on the highly intuitive Python language

Features

The SV2C-PAM4 is a highly integrated 58 Gbps (29 Gbaud) parallel tester that meets the emerging test requirements for 400 Gbe and CEI-56G connectivity applications. Featuring eight independent receivers and eight independent transmitters, the SV2C-PAM4 offers a truly flexible, high-volume, low-cost solution for the test and validation of next generation networking interfaces.

 

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