Title: Advanced MIPI C-PHY/D-PHY Validation (Delivered in Chinese)
Date: Wednesday, April 29, 2020
Time: 10:30 – 11:30 Beijing Time
Overview
Join us for this complimentary Chinese language webinar to learn how to validate advanced MIPI C-PHY/D-PHY interfaces from the physical layer to the functional protocol layer.
Why This Event Is Important
In response to MIPI-CPHY v1.2 date rate up to 3.5Gsps and D-PHY v2.1 data rate up to 4.5Gbps with multi-channel characteristic, the variables required and challenges in the physical layer signal design will increase a lot, from the PCB trace length, jitter, skew alignment, FPC cable length, connectors and so on. From the system-level validation point of view, we will focus on how to validate new specifications of CSI-2 & DSI-2 protocol such as new features of camera and display and how to inject errors to overcome the protocol validation challenge.
Agenda
- Introduction basic MIPI-CPHY/DPHY technology & design challenges
- How to validate Rx capability of MIPI-CPHY/DPHY
- How to test MIPI-CPHY/DPHY Rx conformance test items
- How to validate functionality & compatibility for CSI/DSI devices
- Demonstration
Who Should Attend
Chip designers, Signal validation engineers, Firmware engineers, System application engineers, Field site support engineers
Speakers
Steven Chiang
Senior Field Applications Engineer
Steven Chiang is a high-speed test expert and has 15 years of experience in the implementation and verification of the SerDes interface. As a field application engineer, he has been exposed to the implementation of various MIPI protocols. He has many valuable experience for the design validation and test challenges related to the physical layer (DPHY / DPHY) and the protocol layer (CSI / DSI). He has assisted in successfully deploying MIPI solutions and completing various related verification tests.
Free Registration
Register for this event here.
