Title: DDR5 — Testing Techniques for Emerging DDR5 Standards
Date: Thursday, June 13, 2019
Time: 11:00 – 12:00 EDT
Overview
In this webinar, attendees learned about the new features of the upcoming JEDEC® DDR5 standard and discovered what is necessary to understand in order to successfully design and test DDR5 components and systems.
Why This Event Was Important
There are many new design and test challenges that architects, designers, and test engineers will need to understand in order to take full advantage of the next-generation DDR5 memory interface standard and its sophisticated features. This webinar introduced the key differences in design between DDR4 and DDR5, clarified the new testing requirements being defined by JEDEC, and provided engineers with the solutions to meet these complex DDR5 test standards, including system-level testing and full component-level characterization.
Agenda
- Brief overview of the DDR5 interface and key differences from DDR4
- Facilitating system-level testing on any bench
- Self-contained lab setups for R-DIMM, LR-DIMM, and U-DIMM form factors
- Enabling full component-level characterization of all DDR5 pin groups
- Stimulus generation requirements and command pattern features
- Response analysis requirements and signal capture features
- DDR5 Conformance Test Suite examples
Who Attended
System architects, digital design engineers, verification engineers, product engineers, test engineers, applications engineers, system integrators, product line managers, and project managers.
Speakers
Erin Holley
Senior Digital Designer, Introspect Technology
Erin specializes in digital design and system architecture as part of Introspect Technology’s R&D team.