SV5C Personalized SerDes Tester
The SV5C Personalized SerDes Tester is a highly capable, highly integrated parallel BERT solution that allows for achieving enhanced test coverage and gaining deep insights into multi-channel interface link performance. By simultaneously generating and measuring traffic on 16 lanes and at data rates up to 17 Gbps, the SV5C offers a unique opportunity to characterize SerDes links under realistic system-like conditions while offering world class signal integrity and isolation between channels.
Designed from the ground up to address the validation needs of parallel interfaces such as PCI Express Gen 4 and various upcoming MIPI standards, the SV5C is a technological marvel incorporating innovations in the areas of digital signal processing, analog processing, microwave signal propagation, data analytics, thermal design, and many others!
When used with the Introspect ESP Software, the SV5C becomes an integral part of a complete high-volume characterization station that consists of a test automation suite, device power supplies, device handlers, and device control probes.
- Fully-synthesized integrated jitter injection on 16 lanes
- Fully-automated integrated jitter testing on 16 lanes
- Optimized pattern generator rise-time for receiver stress test applications
- Fully synthesized voltage noise injection on 16 lanes
- Full suite of driver programmability (differential, common-mode, equalization)
- Clock recovery and receiver equalization per lane
- State of the art programming environment based on the highly intuitive Python language
- Integrated device control through SPI, I2C, or JTAG
- Reconfigurable, protocol customization (on request)
Voltage Noise Injection
The SV5C includes per wire voltage noise injection, thus enabling common-mode injection for receiver testing. This also enables difference-mode injection while simultaneously transmitter test traffic at 17 Gbps.
Multi Source Jitter Injection
The SV5C is capable of generating calibrated jitter stress on any data pattern and any output lane configuration. Sinusoidal jitter injection is calibrated in the time and frequency domain in order to generate high-purity stimulus signals.
Conventionally offered as a separate instrument, per-lane pre-emphasis control is integrated on the 16-lane SV5C tester. The user can individually set the transmitter pre-emphasis using a built-in Tap structure. Pre-emphasis allows the user to optimize signal characteristics at the DUT input pins.
Pre-Lane Clock Recovery
Like pre-emphasis, conventional tools often require separate clock recovery instrumentation. In the SV5C, each receiver has its own embedded analog clock recovery circuit. Additionally, the clock recovery is integrated directly inside the receiver’s high-speed sampler, thus offering the lowest possible sampling latency in the industry.