SV3C Personalized SerDes Tester

More integrated; even more productive

The SV3C Personalized SerDes Tester is an ultra-portable, high-performance instrument capable of receiver and transmitter validation at data rates up to 14 Gbps and on up to 32 lanes simultaneously. Like the original SV1C, the SV3C integrates multiple technologies in order to enable the self-contained test and measurement of SerDes interfaces such as PCI Express Gen 3, MIPI M-PHY, or USB3. This highly integrated tester also includes unique reconfiguration and protocol technologies that allow it to tackle advanced protocols such as MIPI C-PHY and MIPI D-PHY.

Key Benefits

  • Highest level of integration at 32 lanes in a handheld form factor
  • Fully-synthesized integrated jitter injection on all lanes
  • Flexible pre-emphasis, equalization, and clock recovery per lane
  • Flexible loopback support per lane
  • State of the art programming environment based on the highly intuitive Python language
  • Single-ended or differential low-speed I/O for digital test vector processing
  • Reconfigurable, protocol customization (on request)

Key Features

Any-Rate Clocking

The SV3C includes internal frequency synthesizers capable of generating any test data rate. Additionally, the SV3C contains reference clock outputs for driving devices under test or generating synchronization references for other equipment. For most applications, all lanes are operated at a single data rate. However, the clock system enables multiple lane clocking configurations depending on the various protocol and multi-site requirements

Burst-Mode BER Testing

Modern SerDes interfaces require complex training sequences and sophisticated power-efficient operating modes. Often called burst-mode, many SerDes transmissions require a new class of Error Detector: one that is able to compute BER on only sections of a non-continuous transmitted data stream. The SV3C includes the optional ability to automatically track intermittent sleep/burst cycles within a test pattern and to measure only relevant payload sections.

Per-Lane Clock Recovery and Unique Dual-Path Architecture

True to the integrated nature of its design, each SV3C receiver has its own embedded analog clock recovery circuit. That is, 32 individual CDR circuits are monolithically integrated in this miniature test system, thus offering the lowest possible sampling latency in a test and measurement instrument. The monolithic nature of the SV3C clock recovery helps achieve wide tracking bandwidth for measuring signals that possess spread-spectrum clocking or very high amplitude wander. Additionally, the SV3C features a dual-path receiver architecture. This unique architecture allows the SV3C to operate as both a digital capture/analysis instrument and an analog measurement instrument. A feature rich clock management system allows for customization of the SV3C to specific customer requirements.