SV3C CPTX 4-Lane MIPI C-PHY Generator

Industry-Leading 4-Lane MIPI C-PHY Generator

The SV3C-CPTX C-PHY Generator is an ultra-portable, high-performance instrument that enables exercising and validating MIPI C-PHY receiver ports. Capable of generating any traffic and being completely data-rate agile, the C-PHY generator includes analog parameter controls that enable gaining deep insights into receiver sensitivity performance and skew/jitter tolerance.

The C-PHY Generator operates using the highly versatile Introspect ESP Software environment. This environment allows for automating receiver tests such as voltage sensitivity or wire-skew tolerance. The environment also includes MIPI pattern compiler tools that enable the generation of complete DSI or CSI packets such as those characteristic of color bars or active image frames.

Key Benefits

  • Any-rate operation and global timing parameter control
  • Per-wire skew injection with < 1 ps resolution
  • Per-wire voltage level control
  • Per-wire LP generation
  • State of the art programming environment based on the highly intuitive Python language
  • Reconfigurable, protocol customization (on request)

Key Features

Block Diagram and Signal Generation Concepts

The SV3C CPTX is a pattern generator capable of creating both LP and HS data streams across four C-PHY lanes simultaneously. The pattern generator architecture offers individual control over LP events, HS events, and global timing events on a per-wire basis. Thus, it provides complete electrical test coverage in a manner similar to AWG solutions while still being versatile enough to generate compliant CSI-2 packets and video frames from within a seamless software environment.

Built into the HS generators within the SV3C CPTX are dedicated hardware C-PHY mapper and encoder circuits. This allows for tremendous ease of use. For example, when defining packet transmissions, the user need not construct wire states or transitions manually (unless he/she so desires) and can just define 16-bit integer payload data.

Burst-Mode Packet Generation & Global Timing Controls

The SV3C CPTX allows for defining every aspect of a packet transmission, yet in a completely seamless manner. Payload data is declared just as that: payload digital data without requiring any knowledge of C-PHY protocol mapping or encoding technology. And if a physical-layer test is required with compliant C-PHY PRBS patterns, such stimulus files are pre-built into the tool for quick selection in the Introspect ESP Software.

Similarly, the SV3C CPTX allows for controlling global timing parameters, and this is useful for automatically verifying HS receiver functionality under various operating conditions. A basic cphyPattern component defines parameters such as preBeginNumUI and postNumUI for varying the timings associated with starting HS transmissions and ending them. Similarly, timing parameters such as lp000Duration allow for varying the preparation (termination enable) period when testing receivers in burst mode.

Full Suite of Analog Parameter Controls

As required by the C-PHY standard, each wire out of the SV3C CPTX generator produces three-level single ended waveforms. The span of the waveform (i.e. distance from the low level to the high level) is defined as voltage swing, and it corresponds to the VOD specification in the C-PHY standard. Additionally, in order to enable receiver stressed eye testing, the generator includes common-mode control in which the entire waveform (low, mid, and high levels) is shifted up or down based on software commands. Similarly, all LP levels are programmable with fine resolution. Such programmability is necessary for enabling various tests related to LP/HS interactions in C-PHY. Finally, advanced options exist for manipulating symmetry of the wire HS voltages (mid level control) and for injecting jitter individually on each wire, and these are all intended to help close the differential eye seen by a receiver.