SV1C Personalized SerDes Tester
Engineered for maximum productivity
The SV1C Personalized SerDes Tester is an ultra-portable, high-performance instrument that creates a new category of tool for high-speed digital product engineering teams. It integrates multiple technologies in order to enable the self-contained test and measurement of complex SerDes interfaces such as PCI Express Gen 3, DisplayPort, Thunderbolt, or MIPI M-PHY.
Coupled with a seamless, easy-to-use development environment, this tool enables product engineers with widely varying skill sets to efficiently work with and develop SerDes verification algorithms. The SV1C fits in one hand and contains 8 independent stimulus generation ports, 8 independent capture and measurement ports and various clocking, synchronization and lane-expansion capabilities. It has been designed specifically to address the growing need of a parallel, system-oriented test methodology while offering world-class signal-integrity features such as jitter injection and jitter measurement.
- Fully-synthesized integrated jitter injection on all lanes
- Fully-automated integrated jitter testing on all lanes
- Optimized pattern generator rise-time for receiver stress test applications
- Flexible loopback support per lane
- Clock recovery per lane
- State of the art programming environment based on the highly intuitive Python language
- Integrated device control through SPI, I2C, or JTAG
- Reconfigurable, protocol customization (on request)
Multi Lane Loop Back
The SV1C is the only bench-top tool that offers instrument grade loopback capability on all differential lanes. The loopback capability of the SV1C includes:
- Retiming of data for the purpose of decoupling DUT receiver performance from DUT transmitter performance
- Arbitrary jitter or voltage swing control on loopback data
Multi Source Jitter Injection
The SV1C is capable of generating calibrated jitter stress on any data pattern and any output lane configuration. Sinusoidal jitter injection is calibrated in the time and frequency domain in order to generate high-purity stimulus signals.
Conventionally offered as a separate instrument, per-lane pre-emphasis control is integrated on the 8-lane SV1C tester. The user can individually set the transmitter pre-emphasis using a built-in Tap structure. Pre-emphasis allows the user to optimize signal characteristics at the DUT input pins.
Pre-Lane Clock Recovery
Like pre-emphasis, conventional tools often require separate clock recovery instrumentation. In the SV1C, each receiver has its own embedded analog clock recovery circuit. Additionally, the clock recovery is integrated directly inside the receiver’s high-speed sampler, thus offering the lowest possible sampling latency in the industry.
Aux Control Port
The SV1C includes a low-speed auxiliary control port that is based on a standard SCSI connector (Figure 7). This port enables controlling DUT registers through JTAG, I2C, or SPI. Additionally, the port includes reconfigurable trigger and flag capability for synchronizing the SV1C with external tools or events.
SV1C, Powered By Introspect ESP
Introspect ESP makes using the SV1C system intuitive and easy. It exploits every capability of the hardware system in order to allow you to be the most efficient at developing your algorithms and test code. Intelligently self-aware, this environment keeps track of every setting that you take the system through, thus never losing track of your every debug step. The show-as-test feature allows you to restore any instrument and device-under-test state even if you have not saved your most recent Test Procedure. Coupled with built-in report generation and a remarkably simple user interface, the Introspect ESP environment allows you to develop, execute, and report on your tests in record time.
- Modular Implementation
- Completely Scripted
- Remarkably Simple