I3C Test and Debug Module
An Introspect SV4E-I3C is a 4-lane complete I3C protocol analyzer/exerciser that connects and autonomously operates as an I3C device thus enabling developers to completely verify their designs and characterize their performance margins. The highly integrated, portable, form factor and software environment allow for unprecedented ease of use when it comes to creating multiple I3C device roles on the bus.
The SV4E-I3C allows high precision timing manipulation with a 5ns resolution for the developer to ensure their designs work over a wide range of device interactions on the bus. It has deep vector memory thus it can be deployed as a MIPI Debug for I3C solution. The SV4E-I3C system has been designed around the MIPI I3C v1.x and I3C Basic 1.x specification standards.
- Self-contained: bus controller with 4 lanes of MIPI I3C ports in an ultra compact form factor operating autonomously
- Flexible: solution featuring I3C and I3C Basic protocol support with real time voltage and timing controls
- Automated: scripting capability ideal for debug tasks, verification and full‐fledged production screening of devices and system boards
- Debug environment: act as a bus slave to become a trace sink with complete readiness for MIPI Debug for I3C
- Device roles: able to configure multiple devices from a single system onto the bus, such as main-master, secondary-masters, and I3C slaves
- Lanes: 4 lanes of SDA/SCL with each lane configured independently
- Timing features: high speed timing manipulation and control to nanosecond resolution for verifying setup and hold times including ACK responses
- I3C protocol features: easily generate CCCs and patterns for private and device-device communication, IBI, and hot-join